Extensive efforts have been made to shrink the cell size in electrically programmable read only memories, called "EPROMs". In general, the smaller the cell size the smaller the integrated circuit die or chip containing a given number of EPROM cells and therefore the higher the yield of useful semiconductor dice in the manufacturing process. Examples of these efforts include the EPROM arrays shown in U.S. Pat. Nos. 4,267,632 and 4,639,893.
An asymmetric memory transistor which eliminates problems of read disturb and drain turn-on is disclosed in an article entitled "A 50-ns 256K CMOS Split-Gate EPROM" by Sahid B. Ali et al., published in the IEEE Journal of Solid State Circuits, Vol. 23, No. 1, February 1988, pp. 79-85. The memory cell disclosed in this article also insures uniform characteristics of each memory transistor across the memory array despite manufacturing tolerances and variations in mask placement. The high read current capable of being used in the cell disclosed in the Ali article gives a speed advantage to the memory array. Another example of an EPROM structure which results in reduced cell size is disclosed in patent application Ser. No. 07/539,657 filed Jun. 13, 1990 on an invention of Boaz Eitan entitled "EPROM Virtual Ground Array" and assigned to WaferScale Integration, Incorporated, the assignee of this invention. Application Ser. No. 07/539,657 is hereby incorporated by reference in its entirety. In application Ser. No. 07/539,657, an electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments which each comprise a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of P floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n.sup.th is an odd integer given by 1.ltoreq.n.ltoreq.N and N+1 is the maximum number of columns in the array, are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate transistors in the n.sup.th column connected to said one segment. The removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor, and the combining of a plurality of select transistors into one select transistor, substantially reduces the area taken by each memory cell in the array.
In the past, to achieve a high-density EPROM array, a virtual ground has been employed. The virtual ground eliminated the space previously taken in the prior art for an electrical contact to the drain region of each transistor in the array because the virtual ground requires only a few spaced electrical contacts. Unfortunately, the virtual ground results in a relatively low speed because of the high capacitance associated with each diffused bit line comprising the virtual ground.
To make a faster array, a different approach was employed wherein a pair of transistors shared a common ground and utilized separate drain diffusions. A plurality of drain diffusions were connected to a metal bit line through contacts as disclosed, for example in U.S. Pat. No. 4,868,629 issued Sep. 19, 1989, and assigned to WaferScale Integration, Inc., the assignee of this application. The resulting circuit was fast because of the use of separate drain diffusions for each of the transistors in the array, but the contacts to the drain diffusions from the overlying metal bit lines took up substantial space and thereby reduced substantially the density of the array. In addition, the diffusion source lines were contacted every eight or sixteen cells by an overlying metal source line. The contacts to the diffusion source lines, and the metal source lines both added substantial area to the array thereby further reducing the density of the array.
Furthermore, memory transistors require a high read current to be fast. To avoid a high read current and the corresponding problems associated therewith, two transistor or four transistor cells were used to generate a differential signal to represent the state of the memory. Unfortunately, two transistor or four transistor cells take substantially more area than a single transistor cell. See, for example, a paper by S. Pathak et al., entitled "A 25ns 16K CMOS PROM using a 420 transistor cell", ISSCC Dig. Tech. Papers, 1985, pp. 162-163.